A New Enhanced Approach to Technology Mapping

An important part of the design flow, technology mapping, expresses logic functions of the netlist using gates from the technology library, in the presence of various design constraints. This paper proposes a new approach to technology mapping, which relies on several known techniques, combined and tuned to work in a new way. The previous work on DAG mapping is extended, by proposing new methods for enumerating mapping choices and performing Boolean matching, which guarantees the delay-optimum phase assignment at the gate boundaries. Two new ways of capturing flexibility in technology mapping are explored and compared: supergates and choice nodes. An experimental technology mapper developed in the MVSIS environment compares favorably with other technology mappers in terms of delay, area, and runtime.